Flip-Chip NIS Cooling Refrigerates a Whole Silicon Chip

NIS tunnel junctions can selectively remove energetic electrons from a normal metal, but cooling the chip’s phonons—the thermal reservoir that matters for attached circuits and sensors—has been harder. The obstacle is not just the junction: heat-carrying quasiparticles must reach a hot-side trap without returning heat across its interface. The authors report a chip-scale refrigerator that treats quasiparticle diffusion and the superconductor-to-trap boundary as design variables, then measures whole-chip phonon cooling below 1 K.

Core Contribution

The device separates the cold-side junction array from the hot-side gold quasiparticle trap with flip-chip bump bonding. That geometry lets quasiparticles diffuse from the cold-side aluminum superconductor toward the rejection side while reducing the interfacial area through which heat can leak backward. The paper’s central claim is therefore architectural rather than a new tunnelling mechanism: controlling where quasiparticles travel and where thermal resistance sits can turn electron cooling into measurable cooling of an entire silicon die.

The reported refrigerator has 1,121 electrically series-connected SINIS pairs, or 2,242 junctions. Its cold-side normal metal is tungsten/titanium-tungsten, the tunnel barrier is aluminum oxide, the superconductor is aluminum, and the trap is gold. Figure 1 shows the two-chip mask layout, normal-metal islands, SINIS pairs, and the nearby phonon and electron thermometers; the photograph makes clear that the cooler is a bump-bonded assembly rather than a suspended microbridge.

Technical Approach

Each SINIS unit filters high-energy electrons through the superconducting gap. The resulting quasiparticles carry the extracted energy within aluminum toward the gold trap. The cross-sectional unit-cell schematic in Figure 2 distinguishes this electrical current path from the quasiparticle heat flow, which is the key distinction behind the design. A colder normal-metal island is useful only if the generated quasiparticles are removed efficiently and the trap does not become a direct thermal short back to the cold side.

The authors use a phonon thermometer on the cold silicon chip and electron thermometers in the normal-metal structures. They also characterize the hot-side thermal path by over-biasing a RuOx thermometer as a heater. The measured temperature rise versus applied power follows a fourth-power thermal-boundary model at 50, 150, 250, and 350 mK, consistent with heat flow limited by dielectric/metal interfaces and the backside connection. This characterization matters because the hot-side temperature is otherwise inferred rather than directly measured during the main cooling sweeps.

Results and Analysis

The strongest result is a 70 mK effective phonon temperature for a 3.9 mm × 3.9 mm × 0.65 mm silicon chip from a 120 mK bath. At a 271 mK rejection temperature, the authors measure a maximum cooling throw of −97 mK, reaching a 174 mK cold-side phonon temperature. The paper compares that throw with −83 mK for a 1 mm suspended silicon island and −97 mK in an earlier membrane-supported SINIS experiment. Matching the latter temperature difference while cooling a full chip, rather than a membrane or microbridge, is the practical advance.

The thermal figures also show that the optimum bias changes with bath temperature. The largest input powers occur at warmer baths, where more hot electrons are available for removal. Under a load-curve measurement at 325 mK, the maximum heat lift is 370 nW with 1.55 μW electrical work input, corresponding to a coefficient of performance of 0.239. The maximum reported second-law efficiency is 2.24% at 275 mK. These are modest refrigeration efficiencies, but they are accompanied by a physical demonstration at the relevant sub-kelvin scale rather than an extrapolation from junction-level electron temperatures.

The measured device is not yet close to full junction utilization. A 309.0 mV current-bias feature, divided by the expected 2,242-junction gap voltage of 0.172 mV, implies an 80.1% working-junction yield; the authors attribute the 19.9% shortfall to shorted junctions. Their model projects that lower-resistance AlOx barriers could increase tunnelling heat transport by 36× and push projected heat lift above 1 mW/cm². That is a design projection, not a demonstrated operating point.

Caveats in Practice

The paper gives direct phonon-temperature evidence and a fitted thermal model, but the hot-side rejection temperature during cooling is calculated from prior thermal-boundary measurements because no RuOx thermometer was installed there for that experiment. Electron cooling exceeds phonon cooling because electron-phonon coupling in each small normal-metal volume is limited. The authors also identify better cold-side coupling, lower electrical contact resistance, and engineered acoustic mismatch at the bump interface as paths to larger throws, potentially several hundred millikelvin. Those are credible engineering directions, but the present evidence establishes a 97 mK throw, not that projected range.