NPUs Run OFDM Baseband Without Baseband Chips

AI-RAN assumes that radio access networks and AI workloads can share compute, but most demonstrations have treated GPUs as the common substrate. This paper asks a narrower hardware question: can an inference-oriented NPU execute wireless baseband processing directly, rather than serving only neural models around the radio stack? The authors answer with a full OFDM transceiver on Huawei Ascend 310B1 NPUs, using USRP X300 devices only as RF front ends.

The paper’s central claim is that AI and baseband workloads share enough matrix-and-vector structure to run on the same NPU engines. Figure 1 frames that claim as computational isomorphism: attention maps, neural weights, OFDM spectra, QAM constellations, and signal waveforms all reduce to primitives that can be scheduled on matrix and vector units.

Core Contribution

The contribution is not that OFDM can be implemented in software; CPUs, DSPs, FPGAs, and GPUs already do that. The new part is the NPU-native rewrite. Traditional baseband code tries to minimize arithmetic count, for example by preferring an FFT butterfly with $O(N \log N)$ work over an explicit DFT matrix with $O(N^2)$ work. On an NPU, that choice can be wrong: a lean algorithm may starve the matrix engine, while a denser formulation fills the hardware.

The authors turn that mismatch into a design rule. Linear baseband operators are restored into matrix form for the Cube engine, nonlinear operators are rewritten as arithmetic chains for the Vector engine, and adjacent operators are fused when intermediate tensors would otherwise round-trip through external memory.

Technical Approach

The implementation maps representative transmit and receive operators onto AscendC kernels. FFT and IFFT become batched DFT matrix multiplications. RRC filtering becomes a Toeplitz matrix multiplication. LDPC encoding and decoding are lifted from bitwise GF(2) operations into int8 generator-matrix multiplication followed by modulo-2 reduction. Least-squares channel estimation is precomputed as a matrix multiplication rather than per-subcarrier division.

For nonlinear pieces, the authors avoid lookup-heavy or scalar-control formulations that fit CPUs better than NPUs. Frame synchronization becomes batched energy detection plus cross-correlation. CFO estimation uses parallel cyclic-prefix autocorrelation. CFO compensation is rewritten from per-sample trigonometric evaluation into a recursive phasor and angle-sum update, keeping the work on vector units. QAM modulation becomes a truncated-scale arithmetic chain; QAM demodulation uses quantize-clamp plus scalar bit extraction.

The other major rewrite is on-chip pipeline fusion. The paper uses LS channel estimation followed by ZF equalization as the example: the channel estimate is produced, consumed, and discarded within one fused kernel. Similar stride-level fusions remove layout conversion between pulse shaping and FFT input, modulation and transform input, and other neighboring stages. The point is practical: on NPUs, moving intermediate tensors through global memory can cost more than the arithmetic itself.

Figure 2 shows the measurement setup: two Orange Pi AI Pro boards, each with an Ascend 310B1 NPU, paired with USRP X300 radios and horn antennas to form a 3.0 GHz SISO over-the-air link.

Results and Analysis

The benchmark compares the same baseband algorithm, with matched matrix dimensions, across an 8 W NPU, a 25 W GPU, a 125 W x86 CPU, and the same-board ARM CPU. End-to-end latency is mixed if judged only in milliseconds: the NPU reaches 30.7 ms transmit and 46.2 ms receive, faster than the GPU at 65.1 ms and 110.2 ms and far faster than the ARM CPU at 255.9 ms and 536.1 ms, but not faster than the 125 W x86 CPU on transmit, where x86 reports 20.6 ms. The energy-normalized result is the stronger case. The NPU reaches 4.1 frames/W on transmit and 2.7 frames/W on receive, compared with 0.6 and 0.4 frames/W for the GPU and 0.4 and 0.1 frames/W for x86.

Operator-level results explain why this is not a blanket NPU win. Some kernels favor the NPU rewrite: receive CFO is 2.8 ms on NPU versus 32.0 ms on GPU and 26.5 ms on x86; RRC downsampling is 2.3 ms versus 12.0 ms and 4.6 ms. Others still favor x86, including transmit RRC upsampling at 2.2 ms on x86 versus 11.7 ms on NPU. The evidence therefore supports a more precise conclusion: NPUs can execute a complete OFDM physical layer efficiently when the algorithms are reformulated around engine occupancy and data movement, but the result depends on operator shape and low-level kernel access.

Caveats

The system is a real over-the-air demonstration, but it is still a narrow one: SISO, 5 MHz sampling, 64-QAM, LDPC(512,256), a 256-point FFT, and one Ascend NPU family with AscendC access. The authors also note that many mainstream NPUs expose only inference runtimes or partial engine access, which limits portability of the method. For radio and edge-AI engineers, the paper is most useful as a mapping recipe and feasibility result, not as proof that any NPU can replace dedicated baseband silicon in deployed RAN equipment.