Surface Code Breaks Error Correction Threshold on Superconducting Chip

A 72-qubit processor achieves a logical error rate of 1.4×10⁻⁴ per correction round, a first for superconducting architectures.

Editorial Desk·March 18, 2024·12 min readstrong

Underlying Paper

Quantum Error Correction Below the Surface Code Threshold

We demonstrate quantum error correction at scale using a distance-7 surface code on a 72-qubit superconducting processor. Our key result is achieving a logical error rate of 1.4×10⁻⁴ per round of error correction, breaking below the surface code threshold for the first time in a superconducting architecture. This is enabled by improved qubit coherence (T₁ > 100μs) and optimized decoder latency.

arXiv:2403.11234Submitted: Mar 15, 2024v1

The pursuit of scalable generative models has driven a wave of architectural innovation, yet the quadratic cost of attention in transformer-based diffusion models remains a fundamental bottleneck. This paper introduces a compelling alternative: replacing the attention backbone entirely with structured state space models (SSMs).

Core Contribution

The authors demonstrate that Mamba-style SSMs can serve as drop-in replacements for attention layers in the U-Net architecture commonly used for diffusion. The key insight is that the selective scan mechanism of modern SSMs naturally captures the multi-scale spatial dependencies required for high-quality image generation.

Technical Approach

The architecture, dubbed DiS (Diffusion with State Spaces), modifies the standard DiT (Diffusion Transformer) by replacing each attention block with a bidirectional SSM layer. The authors introduce a novel "cross-scan" strategy that processes image patches along four spatial directions simultaneously, aggregating the results to capture both local texture and global structure.

Results and Analysis

On ImageNet 256×256 unconditional generation, DiS achieves an FID of 2.67, comparable to DiT-XL/2 (FID 2.27) while requiring 3.2× fewer FLOPs per denoising step. The gap narrows further at 512×512 resolution, where DiS achieves FID 3.41 vs. DiT's 3.04 — a marginal quality difference that may be acceptable given the substantial computational savings.

Training convergence is notably faster: DiS reaches its best FID in approximately 400K steps compared to DiT's 700K steps under identical training budgets. The linear-time scaling also enables generation at resolutions the transformer variant cannot practically reach without additional engineering.

Figures

Evidence Box

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Key Claims

  • Below-threshold logical error rate in superconducting qubits
  • Distance-7 surface code on 72 physical qubits

Key Results

  • Logical error rate: 1.4×10⁻⁴ per round
  • T₁ coherence > 100μs achieved
  • 2.5× improvement over distance-5 code

Limitations & Caveats

  • Single logical qubit demonstrated
  • Decoder optimized for specific noise model
  • Qubit yield not reported

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Readers are encouraged to consult the original arXiv paper for complete details. SOTA Papers does not make claims beyond what is supported by the authors' reported evidence.